Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

VHDL 93

The new features of VHDL'93 are listed below; topic references are given in brackets:

Consistent statement bracketing (Entity, Architecture, Configuration, Package, Component, Procedure, Function, Process, Generate, If, Case, Loop, Record)
Direct instantiation of entities and configurations, avoiding components (Instantiation)
Opening, closing and appending to files (File)
Shared variables (Shared variable)
New attributes, including 'IMAGE and 'PATH_NAME (Attribute name)
Report statement for writing messages (Report)
New shift, rotate and xnor operators (Operator)
Generalized hex and octal bit string literals (String)
Unaffected value in conditional signal assignments (Conditional Assignment, Select)
Variable pulse rejection for inertial delay (Signal assignment)
Postponed processes which execute in the last delta of a simulation time (Process)
Pure and impure functions (Function)
Declarations within generate statements (Generate)
Generalized aliasing, such that anything can be aliased (Alias)
Groups, typically used to pass information to synthesis tools (Group)
Labels on sequential statements (Sequential Statement)
Extended identifiers, allowing any printable character in a name (Name)